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19-2215; Rev 0; 11/01
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis
General Description
The MAX3892 serializer is ideal for converting 4-bitwide, 622Mbps parallel data to 2.5Gbps serial data in DWDM and SONET/SDH applications. A 4 4-bit FIFO allows for any static delay between the parallel output clock and parallel input clock. Delay variation up to a unit interval (UI) is allowed after reset. A fully integrated phase-locked loop (PLL) synthesizes an internal 2.5GHz serial clock from a 622MHz, 155.5MHz, 77.8MHz, or 38.9MHz reference clock. A selectable dual VCO allows excellent jitter performance at both SONET and forward-error correction (FEC) data rates. Operating from a single 3.3V supply, this device accepts low-voltage differential-signal (LVDS) clock and data inputs for interfacing with high-speed digital circuitry, and delivers current-mode logic (CML) serial data and clock outputs. A loopback data output is provided to facilitate system diagnostic testing. The MAX3892 is available in the extended temperature range (-40C to +85C) in a 44-pin QFN package. o Single +3.3V Supply o 455mW Power Consumption o 1.4psRMS Maximum Jitter Generation o 4 4-Bit FIFO Input Buffer o 622Mbps/666Mbps Parallel to 2.5Gbps/2.7Gbps Serial Conversion o 622MHz/667MHz or 311MHz/333MHz Clock Input o On-Chip Clock Synthesizer o Multiple Clock Reference Frequencies: (622.08MHz, 155.52MHz, 77.76MHz, 38.88MHz) or (666.51MHz, 166.63MHz, 83.31MHz, 41.66MHz) o LVDS Parallel Clock and Data Inputs o CML Serial Data and Clock Outputs o Additional CML Output for System Loopback Testing
Features
MAX3892
Applications
SONET/SDH OC-48 Transmission Systems WDM Transponders Add/Drop Multiplexers Dense Digital Cross-Connects Backplane Interconnects
Ordering Information
PART MAX3892EGH TEMP. RANGE -40C to +85C PIN-PACKAGE 44 QFN-EP*
*EP = exposed pad
Typical Application Circuit
LVPECL 100 CZ VCC VCC
RCLKLVDS PDI0+ PDI0SONET/SDH FRAMER
RCLK+ FIL
VCC CLKSET MODE RATESET
SDO+ SDO-
CML
MAX3273
CML SCLKO+ SCLKOSLBEN LASER DRIVER TTL CML
PDI3+ PDI3-
MAX3892
LVDS PCLKI+ PCLKILVDS PCLKO+ PCLKORESET FIFOERROR
SLBPD SLBO+ SLBO-
MAX3882
OPTIONAL FOR SYSTEM LOOPBACK TEST 1:4 DESERIALIZER WITH CDR
LOL
Future product THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE ZO = 50.
________________________________________________________________ Maxim Integrated Products
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+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis MAX3892
ABSOLUTE MAXIMUM RATINGS
Supply Voltage VCC, VCCO, VCCVCO .....................-0.5V to +5V All Inputs and FIL .......................................-0.5V to (VCC + 0.5V) LVDS Output Voltage (PCLKO)................-0.5V to (VCC + 0.5V) CML Output Current (SDO, SCLKO, SLBO) ................22mA Continuous Power Dissipation (TA = +85C) 44-Pin QFN (derate 25mW/C above +85C) ............1625mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V, differential LVDS load = 100 1%, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Supply Current Input Voltage Range Differential Input Voltage Input Common-Mode Current Threshold Hysteresis Differential Input Resistance RIN 83 VCC 1.16 VCC 1.81 VCC - 1.3 >1.0 300 VOH VOL |VOD| |VOD| 1.125 |VOS| 0.925 250 400 25 1.275 25 1900 1.475 LVPECL INPUT SPECIFICATIONS (RCLK) Input High Voltage Input Low Voltage Input Bias Voltage Single-Ended Input Resistance Differential Input Voltage Swing LVDS OUTPUT SPECIFICATIONS (PCLKO) Output High Voltage Output Low Voltage Differential Output Voltage Change in Magnitude of Differential Output Voltage for Complementary States Offset Output Voltage Change in Magnitude of Output Offset Voltage for Complementary States V V mV mV V mV VIH VIL VCC 0.88 VCC 1.48 V V V k mVp-p SYMBOL ICC VI |VID| LVDS input VOS = 1.2V (Note 2) 0 100 61 45 100 117 CONDITIONS MIN TYP 138 MAX 190 2400 UNITS mA mV mV A mV
LVDS INPUT SPECIFICATIONS (PDI[3..0], PCLKI)
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+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V, differential LVDS load = 100 1%, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Differential Output Resistance Output Current Output Current Differential Output Differential Output Resistance Output Common-Mode Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage Input Current VIH VIL IIH IIL VOH VOL IOH = 20A IOL = 1mA Input = 0 or VCC -500 -30 -50 2.4 RL = 50 to VCC 2.0 0.8 +10 +10 VCC 0.4 +500 LVTTL SPECIFICATIONS (RESET, RATESET, SLBEN, SLBPD FIFOERROR, LOL) V V A A V V A Shorted together Shorted to ground RL = 100 differential 640 83 800 100 VCC - 0.2 SYMBOL CONDITIONS MIN 80 TYP MAX 140 12 40 1000 117 UNITS mA mA mVp-p V
MAX3892
CML OUTPUT SPECIFICATIONS (SDO, SCLKO, SLBO)
PROGRAMMING INPUTS (CLKSET, MODE)
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V, differential LVDS loads = 100 1%, CML loads = 50 1%, TA = +25C, unless otherwise noted.) (Note 3)
PARAMETER SYMBOL CONDITIONS RATESET = GND RATESET = VCC MODE = OPEN or VCC MODE = SHORT or 30k to GND tSU tH (Note 4) (Note 4) -94 300 MIN TYP 622 666 622 311 MAX UNITS
PARALLEL INPUT SPECIFICATIONS (PDI, PCLKI) Parallel Input Data Rate Parallel Input Clock Rate Parallel Input Setup Time Parallel Input Hold Time Parallel Clock Output Rise/Fall Time Parallel Clock Output Duty Cycle SERIAL OUTPUT SPECIFICATIONS (SDO, SCLKO) Serial Output Data Rate Serial Data Output Rise/Fall Time Serial Output Clock to Data Delay tr, tf tCLK-Q RATESET = GND RATESET = VCC 20% to 80% (Note 5) -25 2.488 2.666 80 25 Gbps ps ps Mbps MHz ps ps
PARALLEL CLOCK OUTPUT SPECIFICATIONS (PCLKO) tr, tf 20% to 80% 100 46 200 54 ps %
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+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis MAX3892
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V, differential LVDS loads = 100 1%, CML loads = 50 1%, TA = +25C, unless otherwise noted.) (Note 3)
PARAMETER Serial Clock Output Jitter Generation Serial Data Output Random Jitter Serial Data Output Deterministic Jitter SYMBOL JG RJ DJ (Note 7) (Note 6) CONDITIONS MIN TYP 1.2 MAX 1.4 1.4 19 UNITS psRMS psRMS psp-p
REFERENCE CLOCK INPUT SPECIFICATIONS (RCLK) Reference Clock Frequency Tolerance Reference Clock Input Duty Cycle RESET INPUTS (RESET) Minimum Pulse Width of FIFO Reset Tolerated Drift Between PCLKI and PCLKO After Reset UI is PCLKO period UI is PCLKO period 4 1 UI UI 100 30 70 ppm %
Note 1: Note 2: Note 3: Note 4:
Specifications at -40C are guaranteed by design and characterization. Measured with SLBO/CLK622 and SCLK outputs disabled and CML outputs open. AC characteristics are guaranteed by design and characterization. In 622MHz clock mode, the parallel data is clocked in by the rising edge of the 622MHz/666MHz parallel clock input. In the 311MHz clock mode, the parallel data is clocked in on both the rising and falling edges of the clock. The parallel input setup and hold time increases by 60ps if the duty cycle is between 48% to 52% in 311MHz mode (Figure 1). Note 5: Relative to the falling edge of the SCLKO. Note 6: Measurement bandwidth is BW = 12kHz to 20MHz. Note 7: Deterministic jitter includes pattern-dependent jitter and pulse-width distortion. Measured using a 27 - 1 PRBS pattern with 96 consecutive identical digits.
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+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis
Typical Operating Characteristics
(VCC = +3.3V, CML loads AC-coupled to 50 1%, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX3892 toc01
MAX3892
ELECTRICAL EYE DIAGRAM
MAX3892 toc02
POWER-SUPPLY JITTER GENERATION vs. RIPPLE FREQUENCY
35 JITTER GENERATION (psp-p) 30 25 20 15 10 5 50mVp-p 100mVp-p
MAX3892 toc03
170 165 160 SUPPLY CURRENT (mA) 155 150 145 140 135 130 125 120 -40 -20 0 20 40 60 80
40
PATTERN 213-1 PRBS DATA RATE = 2.5Gbps
100
50ps/div
0 10 100 1k 10k RIPPLE FREQUENCY (Hz)
TEMPERATURE (C)
JITTER GENERATION vs. POWER SUPPLY NOISE AMPLITUDE (BW = 2MHz)
MAX3892 toc04
SERIAL-DATA OUTPUT JITTER
MAX3892 toc05
5.0 4.5 JITTER GENERATION (psRMS) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 50 100 150 200
fRCLK = 622MHz
250
NOISE AMPLITUDE (Vp-p)
5ps/div TOTAL WIDEBAND RMS JITTER = 1.3ps PEAK-TO-PEAK JITTER = 15.8ps
Pin Description
PIN 1, 16, 22, 27, 33, 44 2, 5, 8, 11 3 4 6 7 NAME GND VCCO SCLKOSCLKO+ SDOSDO+ Supply Ground Supply Voltage for Outputs +3.3V. Add bypass capacitors near these pins before connecting to the VCC power plane. Negative Serial Clock Output, CML 2.488GHz or 2.666GHz Positive Serial Clock Output, CML 2.488GHz or 2.666GHz Negative Serial Data Output, CML 2.488Gbps or 2.666Gbps Positive Serial Data Output, CML 2.488Gbps or 2.666Gbps FUNCTION
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+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis MAX3892
Pin Description (continued)
PIN 9 10 12 13 14 15 17, 28, 36, 41 18 NAME SLBOSLBO+ SLBPD SLBEN RESET FIFOERROR VCC LOL FUNCTION Negative System Loop-Back Output or 622MHz/666MHz Clock Output. Select CML data or clock as shown in Table 1. Positive System Loop-Back Output or 622MHz/666MHz Clock Output. Select CML data or clock as shown in Table 1. System Loopback Power Down, TTL Input. SLPD = high activates the system loopback output driver; SLBPD = low powers down the loop-back output driver System Loop-Back Enable Input, TTL Input. SLBEN = high activates the system loop-back output; SLBEN = low activates the 622MHz/666MHz reference clock output. FIFO Reset, TTL Input. An active-high reset recenters the FIFO to tolerate maximum skew between PCLKI and PCLKO. FIFO Error Indicator, TTL Output. Active high when the read/write clocks access the same FIFO address. This signal may be used to control RESET. Supply Voltage, +3.3V Loss of Lock, TTL Output. An active low indicates that the VCO and reference frequency differ by 500ppm. Clock Control Input: MODE = GND; fPCLKI = 311.04MHz/333MHz with SCLKO active MODE = 30k to GND; fPCLKI = 311.04MHz/333MHz with SCLKO off MODE = OPEN (float); fPCLKI = 622.08MHz/666MHz with SCLKO off MODE = VCC; fPCLKI = 622.08MHz/666MHz with SCLKO active Positive Parallel Clock, LVDS Input. Data is written to the input register on the clock rising edge in 622Mbps mode and on both rising and falling edges in 311Mbps mode (Figure 1). Negative Parallel Clock, LVDS Input (Figure 1). Positive Data Inputs, LVDS (622Mbps or 666Mbps) Negative Data Inputs, LVDS (622Mbps or 666Mbps) Positive Parallel Clock Output, LVDS. This clock may be 622.08MHz or 666MHz. Negative Parallel Clock Output, LVDS. This clock may be 622.08MHz or 666MHz. Positive Reference Clock Input, LVPECL Negative Reference Clock Input, LVPECL Reference Clock Rate Programming Pin: CLKSET = VCC; RCLK = 622.08MHz/666MHz CLKSET = OPEN (float); RCLK = 155.52MHz/167MHz CLKSET = 30k to GND; RCLK = 77.76MHz/83.3MHz CLKSET = GND; RCLK = 38.88MHz/41.6MHz Data Rate Select, TTL Input. RATESET = high for 2.666Gbps, RATESET = low for 2.488Gbps. PLL Capacitor Pin. Connect a 0.1F capacitor from this pin to VCCVCO. Supply Voltage for VCO +3.3V. Add bypass capacitors near this pin before connecting to the VCC power plane. The exposed paddle must be soldered to ground for proper thermal and electrical operation.
19
MODE
20 21 23, 25, 29, 31 24, 26, 30, 32 34 35 37 38
PCLKI+ PCLKIPDI3+ to PDI0+ PDI3- to PDI0PCLKO+ PCLKORCLK+ RCLK-
39
CLKSET
40 42 43 EP
RATESET FIL VCCVCO Exposed Paddle
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+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis
Detailed Description
The MAX3892 converts 4-bit-wide, 622Mbps/667Mbps data to 2.5Gbps/2.7Gbps serial data (Figure 2). Data is loaded into the 4:1 MUX through a 4 4-bit FIFO buffer for wide tolerance to clock skew. Clock and data inputs are LVDS levels while high-speed serial outputs are CML. An internal PLL frequency synthesizer generates a serial clock from a low-speed reference clock.
PECL Inputs
The reference clock (RCLK+, RCLK-) has PECL inputs for interfacing to a crystal oscillator with AC or DC connections. The RCLK inputs are self-biasing to VCC 1.3V for AC-coupled inputs. Only a 100 differential termination resistance must be added when inputs are AC-coupled.
MAX3892
Current-Mode Logic Outputs
The 2.5Gbps/2.7Gbps data, clock, and system loopback outputs (SDO+, SDO-, SCLKO+, SCLKO-, SLBO+, SLBO-) of the MAX3892 are designed using current-mode logic (CML). The configuration of the MAX3892 CML output circuit includes internal 50 back termination to VCC (Figure 3). These outputs are intended to drive a 50 transmission line terminated with a matched load impedance.
Low-Voltage Differential-Signal Inputs and Outputs
The MAX3892 has LVDS inputs and outputs for interfacing with high-speed digital circuitry. The LVDS standard is based on the IEEE 1596.3 LVDS specification. This technology uses differential low-voltage swings to achieve fast transition times, minimized power dissipation, and noise immunity. For proper operation, the parallel clock LVDS outputs (PCLKO+, PCLKO-) require 100 differential DC termination between the positive and negative outputs. Do not terminate these outputs to ground. The parallel data and parallel clock LVDS inputs (PDI+, PDI-, PCLKI+, PCLKI-) are internally terminated with 100 differential input resistance, and therefore do not require external termination.
FIFO Buffer
Data is latched into the MAX3892 by the parallel input clock PCLKI. The parallel input clock serves as the FIFO write clock. The parallel output clock PCLKO acts as the FIFO read clock that loads the 4:1 MUX. The FIFO allows the read and write clocks to vary by up to 1UI. Conditions that result in the read and write clock accessing the same FIFO address are indicated by
1.608ns DATA IN PDI_ 622MHz CLOCK 311MHz CLOCK TSU TH TSU TH
PCLKI+ - PCLKI-
DATA OUT
SDO
D3
D2
D1
D0
tCLK-Q
SCLKO
2.5GHz CLOCK NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLK0 = (PCLK0+) - (PCLKO-). *PDI3 = D3; PDI2 = D2...PDI0 = D0. PDI3 IS THE MSB AND IS TRANSMITTED FIRST. THIS FIGURE IS NOT INTENDED TO SHOW A SPECIFIC TIMING RELATIONSHIP BETWEEN PARALLEL INPUT DATA AND SERIAL OUTPUT DATA.
Figure 1. Timing Diagram
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+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis MAX3892
Table 1. Loop-Back Operation Mode
SLBPD VIL VIH VIH SLBEN X VIL VIH SLBO OUTPUT Power-Down SLBO Output 622MHz/667MHz Clock Output 2.5Gbps/2.7Gbps System Loop-Back Output MODE RATESET VCC GND VCC GND VCC GND VCC GND
Table 3. Setting the Clock Mode
PCLKI FREQUENCY (MHz) 666Hz 622Hz 666Hz 622Hz 333Hz 311Hz 333Hz 311Hz SCLKO FREQUENCY (GHz) 2.666 2.488 Disabled Disabled Disabled Disabled 2.666 2.488
VCC OPEN 30k to GND GND
Table 2. Setting the Reference Clock Frequency
CLKSET VCC OPEN 30k to GND GND RATESET VCC GND VCC GND VCC GND VCC GND RCLK FREQUENCY (MHz) 666 622 166.5 155.52 83.25 77.76 41.63 38.88
This reference clock can provide a clock hold-over signal to a clock and data recovery (CDR) circuit in the event of loss of signal (LOS).
Design Procedure
Clock Mode Selection
The frequencies of the MAX3892 can be set up using CLKSET, RATESET, and MODE as shown in Tables 2 and 3.
latching high FIFOERROR. To clear this condition, RESET must be asserted high for at least 4UI. FIFOERROR may be tied directly to the RESET input to recenter the FIFO. After reset, the full elastic range of the FIFO is available again.
Layout Techniques
For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Also, use controlled-impedance transmission lines to interface with the MAX3892 clock and data inputs and outputs.
Frequency Synthesizer
The PLL synthesizes a 2.5Gbps/2.7Gbps clock (SCLKO) from an external reference clock. The PLL reference clock (RCLK) may be 622.08MHz/666.53MHz, 155.52MHz/166.6MHz, 77.76MHz/83.3MHz or 38.88MHz/41.65MHz as determined by CLKSET and RATESET. See Table 2 for the reference frequency selection. The parallel output clock PCLKO is also derived from the synthesizer to be SCLKO divided by 4. A TTL-compatible loss-of-lock indicator, LOL, goes low when the VCO is unable to lock to the reference frequency. Frequency difference on RCLK with respect to the divided down SCLKO greater than 500ppm is indicated by a low state on LOL. When the frequency difference between the clocks is less than 250ppm, LOL high indicates a lock condition.
Exposed-Pad Package
The EP 44-pin QFN incorporates features that provide a very low thermal-resistance path for heat removal from the IC to a PC board. The MAX3892's EP must be soldered directly to a ground plane with good thermal conductance.
System Loopback
The MAX3892 is designed to allow system loop-back testing. The loop-back outputs (SLBO+, SLBO-) of the MAX3892 may be directly connected to the loop-back inputs of a deserializer (such as the MAX3882) for system diagnostics. Alternatively, the SLBO pins can be programmed to provide a 622MHz reference clock.
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+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis MAX3892
FIFOERROR RESET
PDI[3..0]+ LVDS PDI[3..0]PCLKI+ LVDS PCLKIPCLKO+ LVDS PCLKO-
4
MAX3892
D SDO+ 4-BIT REG CLK WR/RD CML SLBOSLBPD SLBEN SLBO+ 4x4 FIFO 4:1 MUX CML SDO-
RCLK+ LVPECL RCLK-
FREQUENCY GENERATOR LOGIC
SCLKO+ CML SCLKO-
CLKSET
RATESET
LOL
MODE
Figure 2. Functional Diagram
VCC
VCC
50
50
50
50
OUTPUT CIRCUIT
INPUT CIRCUIT
Figure 3. Current-Mode Logic
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+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis MAX3892
VOD
VOH SINGLE-ENDED OUTPUT |VOD| VOS VOL (VPD+) - (VPD-) DIFFERENTIAL OUTPUT +VOD 0 (DIFF) -VOD VODp-p
Figure 4. Differential Output Levels
Pin Configuration
VCCVCO FIL RATESET CLKSET RCLKGND VCC TOP VIEW PCLKOPCLKO+ RCLK+ VCC
Chip Information
TRANSISTOR COUNT: 6210
44
43
42
41
40
39
38
37
36
35
34
GND VCCO SCLKOSCLKO+ VCCO SDOSDO+ VCCO SLBOSLBO+ VCCO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
MAX3892
GND PDI0PDI0+ PDI1PDI1+ VCC GND PDI2PDI2+ PDI3PDI3+
*THE EXPOSED PADDLE MUST BE SOLDERED TO SUPPLY GROUND ON THE CIRCUIT BOARD.
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SLBEN RESET FIFOERROR GND VCC LOL
QFN
MODE PCLKI+ PCLKIGND
SLBPD
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis
Package Information
QFN 28, 32,44, 48L.EPS
MAX3892
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+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis MAX3892
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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